This invention relates to control of phase shift for a ring oscillator.
A conventional approach for an LC-based ring oscillator uses three LC stages, with a phase shift sum for the three stages being 180xc2x0, as required to support an oscillation. Use of three or four stages is necessary with a conventional approach, because any stage provides a phase shift of less than 90xc2x0, except at certain extreme or unrealistic choices of parameter values. In the simplest three-stage oscillator, each stage provides 60xc2x0 of phase shift. This arrangement is not suitable for applications that require in-phase and quadrature clock signals that are spaced 90xc2x0 apart. Some workers have attempted to handle this problem by providing a four-stage ring oscillator in which each stage provides a 45xc2x0 phase shift. See, for example, J. Savoj and B Razavi, xe2x80x9cA 10 GB/s CMOS Clock and Data recovery Circuit with Frequency Detectionxe2x80x9d, 2001 I.E.E.E. International Solid State Circuits Conference Digest, Technical Paper No. 5.3.
What is needed is an LC-based ring oscillator configuration that provides 90xc2x0, or preferably more, phase shift in each of two stages so that in-phase and quadrature signals, including but not limited to clock signals, can be generated using output signals from two successive stages of the oscillator.
These needs are met by the invention, which uses selected signal buffers plus selected LC circuits to provide additional phase shift in each stage so that, optionally, each stage can provide a 90xc2x0 phase shift without using extreme values to attain this. The additional phase shift is provided by two in-line buffers, incorporated in the forward path, each providing an additional phase shift (estimated to be 0-30xc2x0, depending upon the configuration used).